Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

ABSTRACT

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

CLAIM TO DOMESTIC PRIORITY

The present application is a division of U.S. patent application Ser.No. 13/035,617, filed Feb. 25, 2011, which application is incorporatedherein by reference.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor device and method of forming awafer level chip scale package (WLCSP) using a conductive via and anexposed bump.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products.Semiconductor devices vary in the number and density of electricalcomponents. Discrete semiconductor devices generally contain one type ofelectrical component, e.g., light emitting diode (LED), small signaltransistor, resistor, capacitor, inductor, and power metal oxidesemiconductor field effect transistor (MOSFET). Integrated semiconductordevices typically contain hundreds to millions of electrical components.Examples of integrated semiconductor devices include microcontrollers,microprocessors, charged-coupled devices (CCDs), solar cells, anddigital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such as signalprocessing, high-speed calculations, transmitting and receivingelectromagnetic signals, controlling electronic devices, transformingsunlight to electricity, and creating visual projections for televisiondisplays. Semiconductor devices are found in the fields ofentertainment, communications, power conversion, networks, computers,and consumer products. Semiconductor devices are also found in militaryapplications, aviation, automotive, industrial controllers, and officeequipment.

Semiconductor devices exploit the electrical properties of semiconductormaterials. The atomic structure of semiconductor material allows itselectrical conductivity to be manipulated by the application of anelectric field or base current or through the process of doping. Dopingintroduces impurities into the semiconductor material to manipulate andcontrol the conductivity of the semiconductor device.

A semiconductor device contains active and passive electricalstructures. Active structures, including bipolar and field effecttransistors, control the flow of electrical current. By varying levelsof doping and application of an electric field or base current, thetransistor either promotes or restricts the flow of electrical current.Passive structures, including resistors, capacitors, and inductors,create a relationship between voltage and current necessary to perform avariety of electrical functions. The passive and active structures areelectrically connected to form circuits, which enable the semiconductordevice to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complexmanufacturing processes, i.e., front-end manufacturing, and back-endmanufacturing, each involving potentially hundreds of steps. Front-endmanufacturing involves the formation of a plurality of die on thesurface of a semiconductor wafer. Each die is typically identical andcontains circuits formed by electrically connecting active and passivecomponents. The term “semiconductor die” as used herein refers to boththe singular and plural form of the word, and accordingly can refer toboth a single semiconductor device and multiple semiconductor devices.Back-end manufacturing involves singulating individual die from thefinished wafer and packaging the die to provide structural support andenvironmental isolation.

One goal of semiconductor manufacturing is to produce smallersemiconductor devices. Smaller devices typically consume less power,have higher performance, and can be produced more efficiently. Inaddition, smaller semiconductor devices have a smaller footprint, whichis desirable for smaller end products. A smaller die size can beachieved by improvements in the front-end process resulting in die withsmaller, higher density active and passive components. Back-endprocesses may result in semiconductor device packages with a smallerfootprint by improvements in electrical interconnection and packagingmaterials.

Another goal of semiconductor manufacturing is to produce semiconductordevices with adequate heat dissipation. High frequency semiconductordevices generally generate more heat. Without effective heatdissipation, the generated heat can reduce performance, decreasereliability, and reduce the useful lifetime of the semiconductor device.

Most if not all WLCSPs require a z-direction electrical interconnectstructure for signal routing and package integration. Conventional WLCSPz-direction electrical interconnect structures exhibit one or morelimitations. In one example, a conventional WLCSP contains a flipchiptype semiconductor die and encapsulant formed over the die. Aninterconnect structure is typically formed over, around, and through thesemiconductor die and encapsulant for z-direction vertical electricalinterconnect. The flipchip semiconductor die is electrically connectedto the interconnect structure with bumps or vias. When the vias areformed and plated directly on a pad of the semiconductor die, thesemiconductor die pad can be damaged. Furthermore, the encapsulant andbump interconnect makes package stacking difficult to achieve with finepitch or high input/output (I/O) count electrical interconnect. Inaddition, wire bond type semiconductor die are also difficult to stackwithout dramatically increasing package height. The use of underfillmaterial in packaging the semiconductor die also increases packageheight.

SUMMARY OF THE INVENTION

A need exists for a simple and cost effective WLCSP interconnectstructure for applications requiring low profile packaging with verticalpackage integration and good thermal performance. Accordingly, in oneembodiment, the present invention is a semiconductor device comprising asemiconductor wafer including a plurality of first semiconductor diecomprising an active surface. A plurality of bumps is formed over theactive surface of the first semiconductor die. An encapsulant isdeposited around and over the first semiconductor die including aroundthe bumps. A first conductive via is formed through the encapsulant. Aconductive layer is formed over the encapsulant between the firstconductive via and bumps.

In another embodiment, the present invention is a semiconductor devicecomprising a first semiconductor die and plurality of bumps formed overa first surface of the first semiconductor die. An encapsulant isdeposited around the first semiconductor die and bumps. A firstconductive via is formed through the encapsulant. A conductive layer isformed over the encapsulant between the first conductive via and bumps.

In another embodiment, the present invention is a semiconductor devicecomprising a first semiconductor die and first interconnect structureformed over a first surface of the first semiconductor die. Anencapsulant is deposited around and over the first semiconductor dieincluding around a first portion of the first interconnect structurewhile leaving a second portion of the first interconnect structuredevoid of the encapsulant.

In another embodiment, the present invention is a semiconductor devicecomprising a first semiconductor die and interconnect structure formedover a first surface of the first semiconductor die. An encapsulant isdeposited around the first semiconductor die and around a first portionof the interconnect structure while exposing a second portion of theinterconnect structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a PCB with different types of packages mounted to itssurface;

FIGS. 2 a-2 c illustrate further detail of the semiconductor packagesmounted to the PCB;

FIGS. 3 a and 3 b illustrate a semiconductor wafer with a plurality ofsemiconductor die separated by saw streets;

FIGS. 4 a-4 m illustrate a process of forming WLCSP with conductive viaand an exposed bump;

FIG. 5 illustrates an embodiment of a package on package (PoP) WLCSPincluding a WLCSP with conductive via and an exposed bump;

FIG. 6 illustrates an embodiment of a WLCSP with conductive via and anexposed bump including multiple semiconductor die;

FIG. 7 illustrates an embodiment of WLCSPs with conductive via and anexposed bump stacked back to back to form a PoP WLCSP;

FIG. 8 illustrates an embodiment of a PoP WLCSP including a WLCSP withconductive via and an exposed bump having a heat sink; and

FIG. 9 illustrates an embodiment of a PoP WLCSP including a WLCSP withconductive via and an exposed bump having a redistribution layer (RDL).

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

Semiconductor devices are generally manufactured using two complexmanufacturing processes: front-end manufacturing and back-endmanufacturing. Front-end manufacturing involves the formation of aplurality of die on the surface of a semiconductor wafer. Each die onthe wafer contains active and passive electrical components, which areelectrically connected to form functional electrical circuits. Activeelectrical components, such as transistors and diodes, have the abilityto control the flow of electrical current. Passive electricalcomponents, such as capacitors, inductors, resistors, and transformers,create a relationship between voltage and current necessary to performelectrical circuit functions.

Passive and active components are formed over the surface of thesemiconductor wafer by a series of process steps including doping,deposition, photolithography, etching, and planarization. Dopingintroduces impurities into the semiconductor material by techniques suchas ion implantation or thermal diffusion. The doping process modifiesthe electrical conductivity of semiconductor material in active devices,transforming the semiconductor material into an insulator, conductor, ordynamically changing the semiconductor material conductivity in responseto an electric field or base current. Transistors contain regions ofvarying types and degrees of doping arranged as necessary to enable thetransistor to promote or restrict the flow of electrical current uponthe application of the electric field or base current.

Active and passive components are formed by layers of materials withdifferent electrical properties. The layers can be formed by a varietyof deposition techniques determined in part by the type of materialbeing deposited. For example, thin film deposition can involve chemicalvapor deposition (CVD), physical vapor deposition (PVD), electrolyticplating, and electroless plating processes. Each layer is generallypatterned to form portions of active components, passive components, orelectrical connections between components.

The layers can be patterned using photolithography, which involves thedeposition of light sensitive material, e.g., photoresist, over thelayer to be patterned. A pattern is transferred from a photomask to thephotoresist using light. In one embodiment, the portion of thephotoresist pattern subjected to light is removed using a solvent,exposing portions of the underlying layer to be patterned. In anotherembodiment, the portion of the photoresist pattern not subjected tolight, the negative photoresist, is removed using a solvent, exposingportions of the underlying layer to be patterned. The remainder of thephotoresist is removed, leaving behind a patterned layer. Alternatively,some types of materials are patterned by directly depositing thematerial into the areas or voids formed by a previous deposition/etchprocess using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern canexaggerate the underlying pattern and create a non-uniformly flatsurface. A uniformly flat surface is required to produce smaller andmore densely packed active and passive components. Planarization can beused to remove material from the surface of the wafer and produce auniformly flat surface. Planarization involves polishing the surface ofthe wafer with a polishing pad. An abrasive material and corrosivechemical are added to the surface of the wafer during polishing. Thecombined mechanical action of the abrasive and corrosive action of thechemical removes any irregular topography, resulting in a uniformly flatsurface.

Back-end manufacturing refers to cutting or singulating the finishedwafer into the individual die and then packaging the die for structuralsupport and environmental isolation. To singulate the die, the wafer isscored and broken along non-functional regions of the wafer called sawstreets or scribes. The wafer is singulated using a laser cutting toolor saw blade. After singulation, the individual die are mounted to apackage substrate that includes pins or contact pads for interconnectionwith other system components. Contact pads formed over the semiconductordie are then connected to contact pads within the package. Theelectrical connections can be made with solder bumps, stud bumps,conductive paste, or wirebonds. An encapsulant or other molding materialis deposited over the package to provide physical support and electricalisolation. The finished package is then inserted into an electricalsystem and the functionality of the semiconductor device is madeavailable to the other system components.

FIG. 1 illustrates electronic device 50 having a chip carrier substrateor printed circuit board (PCB) 52 with a plurality of semiconductorpackages mounted on its surface. Electronic device 50 can have one typeof semiconductor package, or multiple types of semiconductor packages,depending on the application. The different types of semiconductorpackages are shown in FIG. 1 for purposes of illustration.

Electronic device 50 can be a stand-alone system that uses thesemiconductor packages to perform one or more electrical functions.Alternatively, electronic device 50 can be a subcomponent of a largersystem. For example, electronic device 50 can be part of a cellularphone, personal digital assistant (PDA), digital video camera (DVC), orother electronic communication device. Alternatively, electronic device50 can be a graphics card, network interface card, or other signalprocessing card that can be inserted into a computer. The semiconductorpackage can include microprocessors, memories, application specificintegrated circuits (ASIC), logic circuits, analog circuits, RFcircuits, discrete devices, or other semiconductor die or electricalcomponents. Miniaturization and weight reduction are essential for theseproducts to be accepted by the market. The distance betweensemiconductor devices must be decreased to achieve higher density.

In FIG. 1, PCB 52 provides a general substrate for structural supportand electrical interconnect of the semiconductor packages mounted on thePCB. Conductive signal traces 54 are formed over a surface or withinlayers of PCB 52 using evaporation, electrolytic plating, electrolessplating, screen printing, or other suitable metal deposition process.Signal traces 54 provide for electrical communication between each ofthe semiconductor packages, mounted components, and other externalsystem components. Traces 54 also provide power and ground connectionsto each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels.First level packaging is a technique for mechanically and electricallyattaching the semiconductor die to an intermediate carrier. Second levelpackaging involves mechanically and electrically attaching theintermediate carrier to the PCB. In other embodiments, a semiconductordevice may only have the first level packaging where the die ismechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging,including bond wire package 56 and flipchip 58, are shown on PCB 52.Additionally, several types of second level packaging, including ballgrid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package(DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quadflat non-leaded package (QFN) 70, and quad flat package 72, are shownmounted on PCB 52. Depending upon the system requirements, anycombination of semiconductor packages, configured with any combinationof first and second level packaging styles, as well as other electroniccomponents, can be connected to PCB 52. In some embodiments, electronicdevice 50 includes a single attached semiconductor package, while otherembodiments call for multiple interconnected packages. By combining oneor more semiconductor packages over a single substrate, manufacturerscan incorporate pre-made components into electronic devices and systems.Because the semiconductor packages include sophisticated functionality,electronic devices can be manufactured using cheaper components and astreamlined manufacturing process. The resulting devices are less likelyto fail and less expensive to manufacture resulting in a lower cost forconsumers.

FIGS. 2 a-2 c show exemplary semiconductor packages. FIG. 2 aillustrates further detail of DIP 64 mounted on PCB 52. Semiconductordie 74 includes an active region containing analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within the die and are electricallyinterconnected according to the electrical design of the die. Forexample, the circuit can include one or more transistors, diodes,inductors, capacitors, resistors, and other circuit elements formedwithin the active region of semiconductor die 74. Contact pads 76 areone or more layers of conductive material, such as aluminum (Al), copper(Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and areelectrically connected to the circuit elements formed withinsemiconductor die 74. During assembly of DIP 64, semiconductor die 74 ismounted to an intermediate carrier 78 using a gold-silicon eutecticlayer or adhesive material such as thermal epoxy or epoxy resin. Thepackage body includes an insulative packaging material such as polymeror ceramic. Conductor leads 80 and bond wires 82 provide electricalinterconnect between semiconductor die 74 and PCB 52. Encapsulant 84 isdeposited over the package for environmental protection by preventingmoisture and particles from entering the package and contaminating die74 or bond wires 82.

FIG. 2 b illustrates further detail of BCC 62 mounted on PCB 52.Semiconductor die 88 is mounted over carrier 90 using an underfill orepoxy-resin adhesive material 92. Bond wires 94 provide first levelpackaging interconnect between contact pads 96 and 98. Molding compoundor encapsulant 100 is deposited over semiconductor die 88 and bond wires94 to provide physical support and electrical isolation for the device.Contact pads 102 are formed over a surface of PCB 52 using a suitablemetal deposition process such as electrolytic plating or electrolessplating to prevent oxidation. Contact pads 102 are electricallyconnected to one or more conductive signal traces 54 in PCB 52. Bumps104 are formed between contact pads 98 of BCC 62 and contact pads 102 ofPCB 52.

In FIG. 2 c, semiconductor die 58 is mounted face down to intermediatecarrier 106 with a flipchip style first level packaging. Active region108 of semiconductor die 58 contains analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed according to the electrical design of the die.For example, the circuit can include one or more transistors, diodes,inductors, capacitors, resistors, and other circuit elements withinactive region 108. Semiconductor die 58 is electrically and mechanicallyconnected to carrier 106 through bumps 110.

BGA 60 is electrically and mechanically connected to PCB 52 with a BGAstyle second level packaging using bumps 112. Semiconductor die 58 iselectrically connected to conductive signal traces 54 in PCB 52 throughbumps 110, signal lines 114, and bumps 112. A molding compound orencapsulant 116 is deposited over semiconductor die 58 and carrier 106to provide physical support and electrical isolation for the device. Theflipchip semiconductor device provides a short electrical conductionpath from the active devices on semiconductor die 58 to conductiontracks on PCB 52 in order to reduce signal propagation distance, lowercapacitance, and improve overall circuit performance. In anotherembodiment, the semiconductor die 58 can be mechanically andelectrically connected directly to PCB 52 using flipchip style firstlevel packaging without intermediate carrier 106.

FIGS. 3 a-3 b and 4 a-4 m illustrate, in relation to FIGS. 1 and 2 a-2c, a process of forming a WLCSP with an RDL formed over an encapsulant,and a molded laser PoP (MLP) or conductive via formed through theencapsulant. The MLP provides vertical interconnect and electricallyconnects to bumps partially exposed from the encapsulant. FIG. 3 a showsa semiconductor wafer 120 with a base substrate material 122, such assilicon, germanium, gallium arsenide, indium phosphide, or siliconcarbide, for structural support. A plurality of semiconductor die orcomponents 124 is formed on wafer 120 separated by saw streets 126 asdescribed above.

FIG. 3 b shows a cross-sectional view of a portion of semiconductorwafer 120. Each semiconductor die 124 has a back surface 128 and activesurface 130 containing analog or digital circuits implemented as activedevices, passive devices, conductive layers, and dielectric layersformed within the die and electrically interconnected according to theelectrical design and function of the die. For example, the circuit caninclude one or more transistors, diodes, and other circuit elementsformed within active surface 130 to implement analog circuits or digitalcircuits, such as digital signal processor (DSP), ASIC, memory, or othersignal processing circuit. Semiconductor die 124 can also contain IPDs,such as inductors, capacitors, and resistors, for RF signal processing.Semiconductor die 124 can also be a flipchip type semiconductor die.

An electrically conductive layer 132 is formed over and extends aboveactive surface 130 such that a top surface of conductive layer 132creates an uneven surface, and has a non-planar topology, with respectto active surface 130. Alternatively, conductive layer 132 is coplanarwith active surface 130. Conductive layer 132 is formed using PVD, CVD,electrolytic plating, electroless plating process, or other suitablemetal deposition process. Conductive layer 132 can be one or more layersof Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductivematerial. Conductive layer 132 operates as contact pads electricallyconnected to the circuits on active surface 130.

FIG. 4 a shows a carrier or substrate 134 containing temporary orsacrificial base material such as silicon, polymer, beryllium oxide, orother suitable low-cost, rigid material for structural support. Aninterface layer or double-sided tape 138 is formed over a top surface136 of carrier 134 as an adhesive bonding film or etch-stop layer. Backsurface 128 of semiconductor wafer 120 is mounted to interface layer 138and over carrier 134.

In FIG. 4 b, an electrically conductive bump material is deposited overconductive layer 132 using an evaporation, electrolytic plating,electroless plating, ball drop, or screen printing process. The bumpmaterial can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinationsthereof, with an optional flux solution. For example, the bump materialcan be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bumpmaterial is bonded to conductive layer 132 using a suitable attachmentor bonding process. In one embodiment, the bump material is reflowed byheating the material above its melting point to form spherical balls orbumps 140. In some applications, bumps 140 are reflowed a second time toimprove electrical contact to conductive layer 132. The bumps can alsobe compression bonded to conductive layer 132. Bumps 140 represent onetype of interconnect structure that can be formed over conductive layer132. The interconnect structure can also use bond wires, conductivepaste, stud bump, micro bump, or other electrical interconnect.

In FIG. 4 c, semiconductor wafer 120 is singulated through saw street126 using a narrow saw blade or laser cutting tool 144. Narrow saw bladeor laser cutting tool 144 penetrates to top surface 136 of carrier 134and removes a portion of interface layer 138, but does not singulate thecarrier.

FIG. 4 d shows opening 146 in semiconductor wafer 120 remains after sawblade or laser cutting tool 144 has removed a portion of thesemiconductor wafer. Opening 146 extends from active surface 130 throughsemiconductor wafer 120 to back surface 128. Opening 146 also extends totop surface 136 of carrier 134 and includes an area previously occupiedby the removed portion of interface layer 138. Opening 146 separatessemiconductor wafer 120 into individual semiconductor die 124. In oneembodiment, semiconductor die 124 are flipchip type semiconductor die.Alternatively, opening 146 can have an increased width, the openingbeing formed with a thick bladed saw, an etching saw, a water jet saw,or other suitable sawing or cutting method.

FIGS. 4 e and 4 f show another method of forming opening 146 with awidth greater than 90 micrometers (um) using a narrow saw blade or lasercutting tool. In FIG. 4 e, semiconductor wafer 120 is shown withsemiconductor die 124 separated by opening 146 that is formed as anarrow opening of less than 90 um. Wafer 120 undergoes a wafer expansionstep to increase the width of opening 146. FIG. 4 e shows semiconductordie 124 being pulled using a wafer expansion table as shown bydirectional arrows 150. The expansion table moves in two-dimensionlateral directions, as shown by arrows 150, to expand the width ofopening 146. The expansion table moves substantially the same distancein the x-axis and y-axis within the tolerance of the table control toprovide separation around a periphery of each die.

In FIG. 4 f, a width of opening 146 has been increased from a width ofless than 90 um to a width greater than or equal to 90 um. As a result,the separation among semiconductor die 124 is increased. Semiconductordie 124 are located farther apart from one another after the expansionthan before the expansion.

Continuing from FIG. 4 d or 4 f, FIG. 4 g shows an encapsulant ormolding compound 152 is deposited over carrier 134, over semiconductordie 124, and within opening 146 using a paste printing, compressivemolding, transfer molding, liquid encapsulant molding, vacuumlamination, spin coating, or other suitable applicator. Encapsulant 152can be polymer composite material, such as epoxy resin with filler,epoxy acrylate with filler, or polymer with proper filler. A firstsurface 154 of encapsulant 152 contacts top surface 136 of carrier 134,a sidewall of semiconductor die 124, active surface 130 of thesemiconductor die, and a portion of conductive layer 132. A secondsurface 156 of encapsulant 152 is planar, substantially parallel to topsurface 136 of carrier 134, and is formed around a portion of bumps 140.Bumps 140 are partially embedded within encapsulant 152, such that aportion of the bumps are devoid of the encapsulant. An end portion ofbumps 140 extends to a height of h1 above second surface 156 ofencapsulant 152. In one embodiment, h1 is greater than 20 um.

Encapsulant 152 is non-conductive and environmentally protects thesemiconductor device from external elements and contaminants. Theformation of encapsulant 152 in contact with the sidewalls ofsemiconductor die 124, and around an active surface 130 of thesemiconductor die leaves back surface 128 of the semiconductor diedevoid of encapsulant resulting in an exposed flipchip structure. Theexposed back surface 128 reduces overall package height as well asproduces improved thermal characteristics for the package. By formingencapsulant 152 over active surface 130 and around bumps 140, the needfor an additional underfill step is eliminated and the package profileis further reduced.

In FIG. 4 h, a plurality of vias 162 is formed in encapsulant 152 bydeep reactive ion etching (DRIE) or laser drilling process. Vias 162 areformed around a perimeter of semiconductor die 124, and extend fromsecond surface 156 through encapsulant 152 to first surface 154 andexpose a portion of carrier 134.

In FIG. 4 i, a plurality of conductive vias or MLP 166 is formed byfilling the plurality of vias 162 with Al, Cu, Sn, Ni, Au, Ag, titanium(Ti), tungsten (W), poly-silicon, or other suitable electricallyconductive material using PVD, CVD, electrolytic plating, electrolessplating process, or other suitable metal deposition process. Conductivevias 166 have a first surface 168 in contact with top surface 136 ofcarrier 134, and a second surface 170 substantially coplanar with secondsurface 156 of encapsulant 152. Alternatively, a plurality of stud bumpsor solder balls can be formed within vias 162. Conductive vias 166provide electrical vertical interconnect to opposing sides of the laterformed WLCSP. Conductive vias 166 provide a reduced package profile byomitting wire bonding which tends to increase package height.Additionally, the formation of conductive vias 166 in encapsulant 152and not over conductive layer 132 avoids possible damage resulting fromforming and plating a conductive via directly on a contact pad of asemiconductor die.

In FIG. 4 j, an electrically conductive layer or RDL 174 is conformallyapplied over conductive vias 166 and encapsulant 152, using a patterningand metal deposition process such as PVD, CVD, sputtering, electrolyticplating, and electroless plating. Conductive layer 174 can be one ormore layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electricallyconductive material. Conductive layer 174 can be one or more conductivelayers including an adhesion layer, barrier layer, and seed or wettinglayer. Conductive layer 174 has a thickness less than a distance betweensecond surface 156 of encapsulant 152 and an end portion of bump 140.Thus, the thickness of conductive layer 174 is less than h1.

Conductive layer 174 electrically connects to second surface 170 ofconductive via 166 and to a portion of bumps 140 free from encapsulant152. Conductive layer 174 can be formed after conductive vias 166 areformed, or alternatively, the conductive layer can be formed with theconductive vias. By indirectly connecting semiconductor die 124 toconductive via 166 through conductive layer 174 and bumps 140, potentialdamage to conductive layer or contact pad 132 is avoided. While acontact pad on a semiconductor die can be damaged due to directlyplating and forming a via on the pad, the formation of conductive via166 does not occur directly on conductive layer or contact pad 132.Instead, conductive via 166 is formed in encapsulant 152 in a peripheryof semiconductor die 124, and electrically connects to the semiconductordie through conductive layer 174 and bumps 140. Thus, the risk ofdamaging conductive layer 132 in establishing vertical interconnectthrough the package is reduced by indirectly connecting conductive via166 to conductive layer 132 through conductive layer 174 and bumps 140.

In FIG. 4 k, carrier 134 is removed by chemical etching, mechanicalpeel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wetstripping to expose first surface 168 of conductive vias 166.Additionally, the plurality of semiconductor die 124 is singulatedthrough encapsulant 152 at saw street 176 using a saw blade or lasercutting tool 178. Saw street 176 is in a periphery region aroundsemiconductor die 124 and between conductive via 166.

FIG. 41 shows a cross sectional view of a semiconductor die 124 havingbeen singulated through saw street 176 to form a WLCSP 180.

FIG. 4 m shows a plan view of WLCSP 180. Second surface 156 ofencapsulant 152 exposes a portion of bumps 140 and second surface 170 ofconductive vias 166. Conductive layer 174 extends between andelectrically connects exposed portions of bumps 140 and second surface170 of conductive vias 166 to provide through vertical interconnectbetween opposing surfaces of WLCSP 180.

Accordingly, WLCSP 180 includes conductive layer or RDL 174 formed overencapsulant 152, and conductive via or MLP 166 formed through theencapsulant for vertical interconnect. Back surface 128 of semiconductordie 124 is devoid of encapsulant, which results in an exposed flipchipstructure. The exposed back surface 128 reduces overall package heightand produces improved thermal characteristics for the package. The useof encapsulant 152 also eliminates the need for an additional underfillstep. Opening 146, in which encapsulant 152 is formed, has a width lessthan 90 um that facilitates advanced nodes. The use of conductive vias166 provides electrical vertical interconnect to opposing sides of WLCSP180 and allows for manufacture at the wafer level, unlike conventionalmulti-stack flipchip designs that include wire bonds. Additionally, byomitting wire bonds in favor of conductive vias 166, the package profileis reduced. By forming conductive vias 166 in encapsulant 152 and notover conductive layer 132, possible damage resulting from forming andplating a conductive via directly on a contact pad of a semiconductordie is avoided. Furthermore, WLCSP 180 facilitates the stacking of anumber of similar WLCSPs, or a multi stack with devices includingdifferent functions, without limiting the I/O count of the deviceswithin the WLCSP.

FIG. 5 shows another embodiment of WLCSP 180, continuing from FIG. 41.In FIG. 5, WLCSP 180 forms a portion of a larger PoP WLCSP 186. PoP 186includes a bond wire WLCSP 188 mounted over and electrically connectedto WLCSP 180 with bumps 190. Bumps 190 are formed by depositingelectrically conductive bump material between first surface 168 ofconductive via 166 and WLCSP 188 using an evaporation, electrolyticplating, electroless plating, ball drop, or screen printing process. Thebump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, andcombinations thereof, with an optional flux solution. For example, thebump material can be eutectic Sn/Pb, high-lead solder, or lead-freesolder. The bump material is bonded between first surface 168 ofconductive via 166 and WLCSP 188 using a suitable attachment or bondingprocess. In one embodiment, the bump material is reflowed by heating thematerial above its melting point to form spherical balls or bumps 190.In some applications, bumps 190 are reflowed a second time to improveelectrical contact to first surface 168 of conductive via 166 and WLCSP188. In one embodiment, bumps 190 are formed over an under bumpmetallization (UBM) having a wetting layer, barrier layer, and adhesivelayer. The bumps can also be compression bonded, and represent one typeof interconnect structure that can be formed between first surface 168of conductive via 166 and WLCSP 188. The interconnect structure can alsouse bond wires, conductive paste, stud bump, micro bump, or otherelectrical interconnect.

WLCSP 188 includes a semiconductor die 194 having a substrate with anactive region containing analog or digital circuits implemented asactive devices, passive devices, conductive layers, and dielectriclayers formed within the die and electrically interconnected accordingto the electrical design and function of the die. For example, thecircuit can include one or more transistors, diodes, and other circuitelements formed within its active surface to implement baseband analogcircuits or digital circuits, such as DSP, ASIC, memory, or other signalprocessing circuit. Semiconductor die 194 can also contain IPDs, such asinductors, capacitors, and resistors, for RF signal processing.

Semiconductor die 194 is mounted over interconnect structure 196 using adie attach adhesive 195. Interconnect structure 196 includes anelectrically conductive layer or RDL 198 formed using a patterning andmetal deposition process such as sputtering, electrolytic plating, andelectroless plating. Conductive layer 198 can be one or more layers ofAl, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductivematerial. Conductive layer 198 is electrically connected to bumps 190and semiconductor die 194. Other portions of conductive layer 198 can beelectrically common or electrically isolated depending on the design andfunction of semiconductor die 124. Interconnect structure 196 furtherincludes an insulation or passivation layer 200 formed around conductivelayer 198 for electrical isolation. The insulation layer 200 containsone or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4),silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide(Al2O3), or other material having similar insulating and structuralproperties. Insulation layer 200 is formed using PVD, CVD, printing,spin coating, spray coating, sintering or thermal oxidation. Portions ofinsulation layer 200 are removed by an etching process to exposeconductive layer 198 for electrical connection to bumps 190 and bondwires 204.

Bond wires 204 are formed between semiconductor die 194 and conductivelayer 198 within interconnect structure 196 to electrically connectsemiconductor die 194 to bumps 190 and WLCSP 180. Bond wires are alow-cost, stable technology for forming the electrical connectionbetween interconnect structure 196 and semiconductor die 194.

An encapsulant or molding compound 206 is deposited over interconnectstructure 196, semiconductor die 194, and around bond wires 204 using apaste printing, compressive molding, transfer molding, liquidencapsulant molding, vacuum lamination, or other suitable applicator.Encapsulant 206 can be polymer composite material, such as epoxy resinwith filler, epoxy acrylate with filler, or polymer with proper filler.Encapsulant 206 is non-conductive, provides physical support, andenvironmentally protects WLCSP 188 from external elements andcontaminants.

FIG. 6 shows another embodiment of a WLCSP including an RDL formed overan encapsulant, and a MLP or conductive via formed through theencapsulant. The MLP provides vertical interconnect and electricallyconnects to bumps partially exposed from the encapsulant. The RDLcontacts a portion of the bumps exposed from the encapsulant.

WLCSP 210 shows a chip stack application including first and secondsemiconductor die. First semiconductor die 214 has a back surface 216and active surface 218. Second semiconductor die 220 has a back surface222 and active surface 224. Active surfaces 218 and 224 contain analogor digital circuits implemented as active devices, passive devices,conductive layers, and dielectric layers formed within the die andelectrically interconnected according to the electrical design andfunction of the die. For example, the circuit can include one or moretransistors, diodes, and other circuit elements formed within activesurfaces 218 and 224 to implement analog circuits or digital circuits,such as DSP, ASIC, memory, or other signal processing circuit.Semiconductor die 214 and 220 can also contain IPDs, such as inductors,capacitors, and resistors, for RF signal processing. An interface layeror double-sided tape 228 contacts back surface 216 of the firstsemiconductor die 214 as an adhesive bonding film or etch-stop layer.Similarly, a die attach adhesive 230 contacts back surface 222 of thesecond semiconductor die 220.

Within WLCSP 210, the second semiconductor die 220 is mounted to thefirst semiconductor die 214 with die attach adhesive 230. Back surface222 of second semiconductor die 220 is mounted to active surface 218 offirst semiconductor die 214 with die attach adhesive 230. Because secondsemiconductor die 220 has an area less than an area of firstsemiconductor die 214, the second semiconductor die covers less than theentire area of active surface 218 of first semiconductor die 214.Accordingly, a portion of active surface 218 in a periphery of firstsemiconductor die 214 is exposed with respect to second semiconductordie 220.

An electrically conductive layer 234 is formed over and extends aboveactive surface 224 such that a top surface of conductive layer 234creates an uneven surface, and has a non-planar topology, with respectto active surface 224. Alternatively, conductive layer 234 is coplanarwith active surface 224. Conductive layer 234 is formed using PVD, CVD,electrolytic plating, electroless plating process, or other suitablemetal deposition process. Conductive layer 234 can be one or more layersof Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductivematerial. Conductive layer 234 operates as contact pads electricallyconnected to the circuits on active surface 224.

An electrically conductive bump material is deposited over conductivelayer 234 using an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The bump material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux solution. For example, the bump material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The bump materialis bonded to conductive layer 234 using a suitable attachment or bondingprocess. In one embodiment, the bump material is reflowed by heating thematerial above its melting point to form spherical balls or bumps 236.In some applications, bumps 236 are reflowed a second time to improveelectrical contact to conductive layer 234. The bumps can also becompression bonded to conductive layer 234. Bumps 236 represent one typeof interconnect structure that can be formed over conductive layer 234.The interconnect structure can also use bond wires, conductive paste,stud bump, micro bump, or other electrical interconnect.

An encapsulant or molding compound 238 is deposited over firstsemiconductor die 214, and second semiconductor die 220 using a pasteprinting, compressive molding, transfer molding, liquid encapsulantmolding, vacuum lamination, spin coating, or other suitable applicator.Encapsulant 238 can be polymer composite material, such as epoxy resinwith filler, epoxy acrylate with filler, or polymer with proper filler.A first surface 240 of encapsulant 238 contacts sidewalls of first andsecond semiconductor die 214 and 220, active surfaces 218 and 224, and aportion of conductive layer 234. A second surface 242 of encapsulant 238is planar, substantially parallel to back surface 216 of firstsemiconductor die 214, and is formed around a portion of bumps 236.Bumps 236 are partially embedded within encapsulant 238, leaving aportion of the bumps free of the encapsulant. An end portion of thebumps 236 extend above second surface 242 of encapsulant 238.Encapsulant 238 is non-conductive and environmentally protects thesemiconductor device from external elements and contaminants.

A plurality of first conductive vias or MLP 244 is formed by firstforming a plurality of first vias in encapsulant 238 by DRIE or laserdrilling process. The plurality of first vias is formed around theperimeter of first semiconductor die 214, and extends from secondsurface 242 through encapsulant 238 to first surface 240. The pluralityof first vias is then filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W,poly-silicon, or other suitable electrically conductive material usingPVD, CVD, electrolytic plating, electroless plating process, or othersuitable metal deposition process to form first conductive vias 244.First conductive vias 244 have a first surface 246 substantiallycoplanar with first surface 240 of encapsulant 238, and a second surface248 substantially coplanar with second surface 242 of encapsulant 238.Alternatively, a plurality of stud bumps or solder balls can be formedwithin the plurality of first vias. First conductive vias 244 provideelectrical vertical interconnect to opposing sides of WLCSP 210. Firstconductive vias 244 provide a reduced package profile by omitting wirebonding which tends to increase package profile. Additionally, theformation of first conductive vias 244 in encapsulant 238 and not overconductive layer 234 avoids possible damage resulting from forming andplating a conductive via directly on a contact pad of a semiconductordie.

A plurality of second conductive vias or MLP 250 is formed by firstforming a plurality of second vias in encapsulant 238 by DRIE or laserdrilling process. The plurality of second vias is formed around theperimeter of second semiconductor die 220, and extends from secondsurface 242 through encapsulant 238 to active surface 218 of firstsemiconductor die 214. The plurality of second vias is then filled withAl, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitableelectrically conductive material using PVD, CVD, electrolytic plating,electroless plating process, or other suitable metal deposition processto form second conductive vias 250. Second conductive vias 250 have afirst surface 252 that contacts active surface 218 of firstsemiconductor die 214, and a second surface 254 substantially coplanarwith second surface 242 of encapsulant 238. Thus, the plurality ofsecond conductive vias 250 has a length less than a length of theplurality of first conductive vias 244. Alternatively, a plurality ofstud bumps or solder balls can be formed within the plurality of secondvias. Second conductive vias 250 provide electrical verticalinterconnect to first semiconductor die 214. Second conductive vias 250also provide a reduced package profile by omitting wire bonding whichtends to increase package profile.

An electrically conductive layer or RDL 258 is conformally applied overfirst conductive vias 244, second conductive vias 250, and encapsulant238, using a patterning and metal deposition process such as PVD, CVD,sputtering, electrolytic plating, and electroless plating. Conductivelayer 258 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or othersuitable electrically conductive material. Conductive layer 258 can beone or more conductive layers including an adhesion layer, barrierlayer, and seed or wetting layer. Conductive layer 258 has a thicknessless than a distance between second surface 242 of encapsulant 238 andan end portion of bumps 236. Conductive layer 258 electrically connectsto second surface 248 of first conductive via 244, second surface 254 ofsecond conductive via 250, and to a portion of bumps 236 free fromencapsulant 238, thereby providing electrical interconnect between firstsemiconductor die 214, second semiconductor die 220, and semiconductordevices external to WLCSP 210.

FIG. 7 shows another embodiment of a WLCSP including an RDL formed overan encapsulant, and a MLP or conductive via formed through theencapsulant. The MLP provides vertical interconnect and electricallyconnects to bumps partially exposed from the encapsulant. The RDLcontacts a portion of the bumps exposed from the encapsulant.

PoP WLCSP 270 shows a dual-sided application including a first WLCSP180, from FIG. 41, mounted to a second WLCSP 272 similar to WLCSP 180.WLCSP 272 includes a semiconductor die 276 having a substrate with anactive region containing analog or digital circuits implemented asactive devices, passive devices, conductive layers, and dielectriclayers formed within the die and electrically interconnected accordingto the electrical design and function of the die. For example, thecircuit can include one or more transistors, diodes, and other circuitelements formed within its active surface to implement baseband analogcircuits or digital circuits, such as DSP, ASIC, memory, or other signalprocessing circuit. Semiconductor die 276 can also contain IPDs, such asinductors, capacitors, and resistors, for RF signal processing.

Semiconductor die 276 is mounted to semiconductor die 124, back surface278 to back surface 128, with die attach adhesive 274. Semiconductor die124 has an area that is substantially equal to an area of semiconductordie 276, such that sidewalls of semiconductor die 124 substantiallyalign with sidewalls of semiconductor die 276. Alternatively,semiconductor die 124 and 276 can have areas of different sizes. Forexample, semiconductor die 124 can have an area less than an area ofsemiconductor die 276, such that semiconductor die 124 covers less thanthe entire area of bottom surface 278 of semiconductor die 276.Alternatively, semiconductor die 124 can have an area greater than anarea of semiconductor die 276, such that semiconductor die 276 coversless than the entire area of bottom surface 128 of semiconductor die124. Regardless of the relative sizing of semiconductor die 124 and 276,the semiconductor die are configured for the subsequent alignment oflater formed conductive vias in the periphery of the semiconductor die.

WLCSP 272 includes an electrically conductive layer 284 formed over andextending above active surface 280 such that a top surface of conductivelayer 284 creates an uneven surface, and has a non-planar topology, withrespect to active surface 280. Alternatively, conductive layer 284 iscoplanar with active surface 280. Conductive layer 284 is formed usingPVD, CVD, electrolytic plating, electroless plating process, or othersuitable metal deposition process. Conductive layer 284 can be one ormore layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electricallyconductive material. Conductive layer 284 operates as contact padselectrically connected to the circuits on active surface 280.

An electrically conductive bump material is deposited over conductivelayer 284 using an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The bump material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux solution. For example, the bump material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The bump materialis bonded to conductive layer 284 using a suitable attachment or bondingprocess. In one embodiment, the bump material is reflowed by heating thematerial above its melting point to form spherical balls or bumps 286.In some applications, bumps 286 are reflowed a second time to improveelectrical contact to conductive layer 284. The bumps can also becompression bonded to conductive layer 284. Bumps 286 represent one typeof interconnect structure that can be formed over conductive layer 284.The interconnect structure can also use bond wires, conductive paste,stud bump, micro bump, or other electrical interconnect.

An encapsulant or molding compound 290 contacts encapsulant 152 of WLCSP180, and is deposited over semiconductor die 276 using a paste printing,compressive molding, transfer molding, liquid encapsulant molding,vacuum lamination, spin coating, or other suitable applicator.Encapsulant 290 can be polymer composite material, such as epoxy resinwith filler, epoxy acrylate with filler, or polymer with proper filler.A first surface 292 of encapsulant 290 contacts sidewalls ofsemiconductor die 276, active surface 280, and a portion of conductivelayer 284. A second surface 294 of encapsulant 290 is planar,substantially parallel to back surface 278 of semiconductor die 276, andis formed around a portion of bumps 286. Bumps 286 are partiallyembedded within encapsulant 290, leaving a portion of the bumps free ofthe encapsulant. An end portion of the bumps 286 extend above secondsurface 294 of encapsulant 290. Encapsulant 290 is non-conductive andenvironmentally protects semiconductor die 276 from external elementsand contaminants.

A plurality of conductive vias or MLP 298 is formed by forming aplurality of vias in encapsulant 290 by DRIE or laser drilling process.The plurality of vias is formed around the perimeter of semiconductordie 276, and extend from second surface 294 through encapsulant 290 tofirst surface 292. The plurality of vias is then filled with Al, Cu, Sn,Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electricallyconductive material using PVD, CVD, electrolytic plating, electrolessplating process, or other suitable metal deposition process to formconductive vias 298. Alternatively, a plurality of stud bumps or solderballs can be formed within the plurality of vias to form conductive vias298. Conductive vias 298 have a first surface 300 that aligns with, andelectrically connects to, conductive vias 166 of WLCSP 180. Conductivevias 298 have a second surface 302 that is coplanar with second surface294 of encapsulant 290. Therefore, conductive vias 298 provideelectrical vertical interconnect to opposing sides of WLCSP 272.Conductive vias 298 also provide a reduced package profile by omittingwire bonding which tends to increase package profile. The formation ofconductive vias 298 in encapsulant 290 and not over conductive layer 284avoids possible damage resulting from forming and plating a conductivevia directly on a contact pad of a semiconductor die.

An electrically conductive layer or RDL 306 is conformally applied oversecond surface 302 of conductive vias 298 and second surface 294 ofencapsulant 290, using a patterning and metal deposition process such asPVD, CVD, sputtering, electrolytic plating, and electroless plating.Conductive layer 306 can be one or more layers of Al, Cu, Sn, Ni, Au,Ag, or other suitable electrically conductive material. Conductive layer306 can be one or more conductive layers including an adhesion layer,barrier layer, and seed or wetting layer. Conductive layer 306 has athickness less than a distance between second surface 294 of encapsulant290 and an end portion of bumps 286. Conductive layer 306 electricallyconnects to second surface 302 of conductive via 298 and to a portion ofbumps 286 free from encapsulant 290, thereby providing electricalinterconnect among semiconductor die 124, semiconductor die 276, andsemiconductor devices external to WLCSP 270.

FIG. 8 shows another PoP WLCSP 310, similar to PoP 186 from FIG. 5. InFIG. 8, PoP 310 has a thermal interface material (TIM) 314, and heatspreader or heat sink 316. TIM 314 is a thermal epoxy, thermal epoxyresin, or thermal conductive paste that is formed on back surface 128 ofsemiconductor die 124. Heat spreader 316 is mounted to semiconductor die124 with TIM 314. Heat spreader 316 can be Cu, Al, or other materialwith high thermal conductivity. TIM 314 and heat spreader 316 form athermally conductive path that aids with distribution and dissipation ofheat generated by semiconductor die 124 and increases the thermalperformance of WLCSP 310.

FIG. 9 shows another PoP WLCSP 320, similar to PoP 186 from FIG. 5. InFIG. 9, PoP 320 has a conductive layer or RDL 322 that is conformallyapplied over back surface 128, interface layer 138, encapsulant 152, andconductive vias 166. Conductive layer 322 is formed using a patterningand metal deposition process such as PVD, CVD, sputtering, electrolyticplating, and electroless plating. Conductive layer 322 can be one ormore layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electricallyconductive material. Conductive layer 322 can be one or more conductivelayers including an adhesion layer, barrier layer, and seed or wettinglayer. Conductive layer 322 contacts and electrically connects to firstsurface 168 of conductive via 166 and to bumps 190. In PoP 320,interconnect structure 196 and bumps 190 form a BGA including multipleinterconnect points that are electrically connected to conductive layer322 according to the electrical design of PoP 320. By electricallyconnecting bumps 190 to interconnect structure 196 and conductive layer322, semiconductor die 194 is electrically connected to conductive via166, conductive layer 174, bumps 140, semiconductor die 124, andsemiconductor devices external to WLCSP 320.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A semiconductor device, comprising: a semiconductor wafer including aplurality of first semiconductor die comprising an active surface; aplurality of bumps formed over the active surface of the firstsemiconductor die; an encapsulant deposited around and over the firstsemiconductor die including around the bumps; a first conductive viaformed through the encapsulant; and a conductive layer formed over theencapsulant between the first conductive via and bumps.
 2. Thesemiconductor device of claim 1, wherein a portion of the bumps isdevoid of the encapsulant.
 3. The semiconductor device of claim 1,further including a second semiconductor die disposed over the firstsemiconductor die.
 4. The semiconductor device of claim 3, furtherincluding a second conductive via formed through the encapsulant betweenthe conductive layer and second semiconductor die.
 5. The semiconductordevice of claim 1, further including a heat spreader disposed over thefirst semiconductor die.
 6. The semiconductor device of claim 1, furtherincluding a plurality of stacked semiconductor devices electricallyconnected through the first conductive via.
 7. A semiconductor device,comprising: a first semiconductor die; a plurality of bumps formed overa first surface of the first semiconductor die; an encapsulant depositedaround the first semiconductor die and bumps; a first conductive viaformed through the encapsulant; and a conductive layer formed over theencapsulant between the first conductive via and bumps.
 8. Thesemiconductor device of claim 7, wherein a portion of the bumps isdevoid of the encapsulant.
 9. The semiconductor device of claim 7,further including a second semiconductor die disposed over the firstsemiconductor die.
 10. The semiconductor device of claim 9, furtherincluding a second conductive via formed through the encapsulant betweenthe conductive layer and second semiconductor die.
 11. The semiconductordevice of claim 9, further including an interconnect structure disposedbetween the first semiconductor die and second semiconductor die. 12.The semiconductor device of claim 7, further including a heat spreaderdisposed over the first semiconductor die.
 13. The semiconductor deviceof claim 7, further including a plurality of stacked semiconductordevices electrically connected through the first conductive via.
 14. Asemiconductor device, comprising: a first semiconductor die; a firstinterconnect structure formed over a first surface of the firstsemiconductor die; and an encapsulant deposited around and over thefirst semiconductor die including around a first portion of the firstinterconnect structure while leaving a second portion of the firstinterconnect structure devoid of the encapsulant.
 15. The semiconductordevice of claim 14, further including a conductive via formed throughthe encapsulant.
 16. The semiconductor device of claim 15, furtherincluding a conductive layer formed over the encapsulant between theconductive via and first interconnect structure.
 17. The semiconductordevice of claim 15, further including a plurality of stackedsemiconductor devices electrically connected through the conductive via.18. The semiconductor device of claim 14, wherein the first interconnectstructure includes a bump.
 19. The semiconductor device of claim 14,further including a second semiconductor die disposed over the firstsemiconductor die.
 20. The semiconductor device of claim 19, furtherincluding a second interconnect structure disposed between the firstsemiconductor die and second semiconductor die.
 21. A semiconductordevice, comprising: a first semiconductor die; an interconnect structureformed over a first surface of the first semiconductor die; and anencapsulant deposited around the first semiconductor die and around afirst portion of the interconnect structure while exposing a secondportion of the interconnect structure.
 22. The semiconductor device ofclaim 21, further including: a conductive via formed through theencapsulant; and a conductive layer formed over the encapsulant andelectrically connected to the conductive via and interconnect structure.23. The semiconductor device of claim 22, further including a pluralityof stacked semiconductor devices electrically connected through theconductive via.
 24. The semiconductor device of claim 21, wherein theinterconnect structure includes a bump.
 25. The semiconductor device ofclaim 21, further including a second semiconductor die disposed over thefirst semiconductor die.